1. Field of the Invention
The present invention relates to a timing analysis apparatus and a method of timing analysis, and particularly to a timing analysis apparatus and a method of timing analysis considering influences of a power supply/ground noise.
2. Description of Related Art
The influences of a power supply/ground noise is becoming more and more apparent, designing a high-speed logical circuit. Especially a jitter of a clock signal input to the logical circuit (the jitter of the clock signal hereinafter merely referred to as a jitter) is conventionally known as one of the influences of the power supply/ground noise. The jitter is an important design index in a circuit generating a high-speed signal such as a PLL (Phase Locked Loop), DLL (Delay Locked Loop), USB (Universal Serial Bus), and DDR I/F (Double Data Rate I/F).
Conventionally analysis and design with a consideration over the jitter have been performed in a timing analysis in a circuit design so as to prevent from a malfunction in the logical circuit due to the power supply/ground noise.
However in recent years, circuit design is becoming more complicated along with higher speed of the logical circuit. Further, a level of designing the logical circuit becomes higher and higher, it is more difficult to design a logical circuit that satisfies the design index considering the jitter. Therefore, a more appropriate method to consider the jitter has been demanded.
There are known two jitters generated in a clock signal (operational clock) supplied to the logical circuit, which are a period jitter and a timing jitter. The period jitter and timing jitter are described hereinafter in detail with reference to FIGS. 22A to 22C. FIG. 22A is a basic cycle of the clock signal. FIG. 22B is the period jitter for deviation of clock signals. FIG. 22C is the timing jitter for deviation of clock signals.
As shown in FIG. 22B, the period jitter is a jitter generated between adjacent edges or two clock edges of a constant interval, and a maximum value of an amount of deviation from the basic cycle aggregated by each edge. As shown in FIG. 22C, the timing jitter expresses a blur width of an edge generated for a long time.
FIG. 23 is a configuration of a conventional timing analysis apparatus. In the conventional analysis apparatus, a power supply/ground noise waveform is stored at a power supply/ground noise waveform storage unit 901. A power supply voltage calculation unit 902 calculates power supply voltage information based on the power supply/ground noise waveform and store it to a power supply voltage information storage unit 903.
A delay time calculation unit 906 calculates delay information based on the power supply voltage information and the netlist and a delay library. And the delay time calculation unit 906 stores the delay information to a delay information storage unit 907. Incidentally, the netlist is stored in a netlist storage unit 904. The delay library is stored in a delay library storage unit 905. Timing constraint information is stored in a timing constraint storage unit 908. A timing analysis unit 909 performs a timing analysis according to the timing constraint and the delay information. Then the timing analysis unit 909 stores a result of the analysis to a timing analysis result storage unit 910.
In a conventional timing analysis apparatus, a timing jitter value is used to consider the influence of the power supply/ground noise to timings. A timing window (not shown) may be used together.
The power supply voltage calculation unit 902 calculates a maximum value VMAX and a minimum value VMIN between a power supply (VDD) and a ground (VSS) from the power supply/ground noise waveform using:
                              V          MAX                =                                            MAX                              t                =                                  -                  ∞                                            ∞                        ⁡                          (                                                                    V                    DD                                    ⁡                                      (                    t                    )                                                  -                                                      V                    SS                                    ⁡                                      (                    t                    )                                                              )                                ⁢                                          ⁢          and                                    (                  Equation          ⁢                                          ⁢          1                )                                                      V            MIN                    =                                    MIN                              t                =                                  -                  ∞                                            ∞                        ⁡                          (                                                                    V                    DD                                    ⁡                                      (                    t                    )                                                  -                                                      V                    SS                                    ⁡                                      (                    t                    )                                                              )                                      ,                            (                  Equation          ⁢                                          ⁢          2                )            and creates power supply voltage information. Further, when using the timing window together, time range to refer to the maximum value VMAX and the minimum value VMIN is limited depending on the time range.
Further, the delay time calculation unit 906 refers to the power supply voltage information, and calculates a maximum value TMAX and a minimum value TMIN of a delay time that corresponds to the maximum value VMAX and the minimum value VMIN of the power supply voltage value, using:TMAX=f(VMAX, AnotherParameters . . . )  (Equation 3)andTMIN=f(VMIN, AnotherParameters . . . ),  (Equation 4)and generates the delay information. The delay information includes a delay time in a logical cell or a register cell, a delay time between cells (lines), a setup time or a hold time of the register cell and so on.
Further, the timing analysis unit 909 performs the timing analysis using the delay time included in the delay information. At this time the maximum value TMAX and the minimum value TMIN of the delay time are combined in a way that a result of the timing analysis becomes a worst case. The timing analysis unit 909 considers the influence of the power supply/ground noise in this manner. In the timing analysis, a setup analysis for analyzing that a signal is delivered before a subsequent clock, and a hold analysis for analyzing that a signal is delivered after a current clock are performed.
FIG. 24A is an example of the Setup analysis. FIG. 24B is an example of the Hold analysis. In this example, a path diverges to P901 and P902 after clock path 3. The two paths P901 and P902 are input in common to a register 2. As shown in FIG. 24A, the maximum value TMAX of the delay time is used to the path P901 that passes clock path 1, register 1, data path 1, the register 2 in this order. The minimum value TMIN of the time delay is used to the path P902 that passes clock path 2, the register 2 in this order. Further as shown in FIG. 24B, contrary to the setup analysis, the minimum value TMIN of the delay time is used to the path P901, and the maximum value TMAX of the delay time is used to the path P902 in the hold analysis.
As a conventional timing analysis apparatus, techniques disclosed in Japanese Unexamined Patent Application Publication No. 2005-092885 and Japanese Unexamined Patent Application Publication No. 2005-141434 are known.
As described in the foregoing, with a consideration over the influence of the power supply/ground noise, only the timing jitter has been covered as in equations 1 to 4 in the timing verification, because the timing jitter can be easily calculated from the power supply/ground noise jitter waveform.
However it has now been discovered that using the timing jitter in the timing verification of the logical circuit decreases verification accuracy (analysis accuracy) of the timings and also hinders from speeding up the logical circuit. That is, using the timing jitter in the timing verification could lead to misjudging a timing violation where no timing violation occurs actually. This creates a strict analysis that a timing violation is easily determined, thereby making it difficult to speed up the logical circuit.